Schutt-Aine wins Best Paper Award at EDAPS 2013

2/24/2014 Mark Pajor, ECE ILLINOIS

ECE Professor Jose E. Schutt-Aine received the Best Paper Award at EDAPS 2013, the IEEE Electrical Design of Advanced Packaging & Systems Symposium.

Written by Mark Pajor, ECE ILLINOIS

ECE Professor Jose E Schutt-Aine received the Best Paper Award at EDAPS 2013, the IEEE Electrical Design of Advanced Packaging & Systems Symposium. The symposium took place in Nara, Japan. He won the award for his paper titled, “Comparing Fast Convolution and Model Order Reduction Methods for S-Parameter Simulation.” Simulation is integral to the design of circuits, as it allows the designer to quickly, efficiently, and economically characterize a circuit before physically producing it.

Jose E Schutt-Aine
Jose E Schutt-Aine

Schutt-Aine co-authored it with Patrick Goh, a former graduate student under Schutt-Aine who is now a professor at the Universiti Sains Malaysia. The paper explores both the fast convolution and model order reduction methods for characterizing circuits, determining the advantages and disadvantages of each method in terms of accuracy and computational speed.

The current standard for simulating large circuits is model order reduction, which allows the characterization of circuits based on a small portion of the circuit’s variables, rather than going through the traditionally impractical process of examining every variable.

“Model order reduction is interesting because it allows you to avoid the convolution process, which is slow,”Schutt-Aine said. “But we came up with a way of approximating responses so that we can use fast convolution.”

While model order reduction became the industry standard because of its increased speed over the typical convolution process, Schutt-Aine and Goh used S-Parameters in order to facilitate an accelerated convolution process. With a fast convolution process newly available, Schutt-Aine and Goh saw the value in comparing it against the accepted standard.

Schutt-Aine and Goh put the two methods to the test. The results showed that the S-Parameter fast convolution method can be faster to simulate and easier to implement than the industry standard model order reduction method, particularly when a chip has a large number of ports.

Schutt-Aine and Goh’s paper is important because the modeling community has lacked proper analyses of these two methods until now.

“A lot of people are using either one method or the other for commercial applications, but they don’t really have a good assessment of the advantages of each,” he said. “Now you really get to see the advantages and disadvantages of both methods.”

Schutt-Aine hopes that with their new data, researchers will make more informed decisions when modeling circuits, and that they will see the advantages of fast convolution S-Parameter simulation and consider using it over the industry standard. Schutt-Aine and Goh’s research could make the work of circuit researchers and designers more accurate and efficient.

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This story was published February 24, 2014.