Hu and Vasudevan receive NSF CAREER Awards

ECE Assistant Professors Yih-Chun Hu and Shobha Vasudevan are 2010 recipients of the Faculty Early Career Development (CAREER) Award from the National Science Foundation (NSF). These awards are among the most prestigious given to young faculty.

Hu and Vasudevan join Alejandro Dominguez-Garcia and Eric Pop, who received CAREER Awards earlier this year, and bring the total ECE professors who won the award this year to four. In addition, Hu and Vasudevan are both researchers in the Coordinated Science Lab.

Hu’s proposal focuses on the problem of layer-violating attacks in computer security. Networks were not designed to be secure. The functionality of networks is divided into several layers. For example, wireless networks consist of a physical layer, a data link or MAC layer, a networking layer, a transport layer, and the applications.

“Since the problem of security has started to become an issue in wireless networks, people have tried to secure these layers individually,” Hu said. “The problem is that they have to rely on everything below a layer being secure.”

When building a secure higher layer protocol, everything underneath must be secure. If not, it is like building on a shaky foundation—the lower layers are more vulnerable.

“One of the things that we’ll be trying to work on is building these interlocking pieces so that each lower layer supports the layer above it by providing all the properties that it needs,” Hu said. “When you get to the top of the protocol stack, you have some meaningful guarantee that you can make.”

Hu will also work with the problem of privacy. This is particularly an issue for vehicular ad hoc networks (VANETs), which are used to allow vehicles to interact. Each vehicle’s precise location and speed information is given. If a collision is imminent, VANETs will warn the drivers. Vehicle identification can be a source of privacy compromise, and there have been several schemes to reduce the number of privacy compromises leaked by VANET messages.

Hu’s proposal also included an educational component. He will target students—especially those in middle school—to consider computing and computer security.

“I think a lot of students will fall behind in math and sciences in middle school,” Hu said. “It becomes very difficult for them to pursue an engineering career because we start out requiring such a high level of math.”

Hu plans to expose students to hands-on lab experience to solve a variety of engineering problems. He hopes to involve undergraduates to present problems that their engineering disciplines solve in a demonstration similar to those at Engineering Open House.

“Hopefully, that would spark an interest in thinking that engineering, math, and science can actually be used to solve cool problems that we maybe didn’t relate to being math, science, and engineering types of problems,” he said.

Hu views the program as a summer program for now, but envisions it as something that could evolve into a middle school elective course.

Vasudevan was excited to learn about receiving the award. “I am thrilled and honored by this recognition, but I also feel responsible to meet the high expectations set by the award in pursuing my research goals,” she said.

Vasudevan’s proposal addressed the automatic generation of system verification artifacts called assertions. Assertions are widely used throughout the semiconductor design cycle, which applies assertions at multiple stages in the design. Since design and verification engineers manually code and write these assertions, design verification is a serious bottleneck that consumes disproportionately high time and resources.

"Just the fact that there are so many man hours that are lost in assertion-based verification is a good reason to automate this process,” Vasudevan said.

GoldMine is the assertion generation tool developed by Vasudevan and her research group. GoldMine generates assertions by combining data mining and formal verification technologies. Data mining generates a lot of information about a system, but it cannot understand this information in the context of the system. Conversely, formal verification has a total understanding of the system, but is computationally inefficient.

"Combining these two technologies ends up offsetting each others' disadvantages, and the synergy between these two technologies adds up to a whole that is greater than the sum of its parts,” Vasudevan said.

In addition to assertion generation, GoldMine has been applied to test generation in the design verification phase. GoldMine has managed to achieve test coverage closure, providing a metric for test completeness to designers. In doing this, GoldMine solves a problem that has been an open challenge to the design verification/validation community for decades.

Vasudevan’s proposal also had an innovative educational component. During her own engineering education, she noticed that workshops to enable women in engineering/sciences interact, were scarce and inaccessible.

“When I was a graduate student, I used to want to meet other women like myself, because it was getting tiresome being the only female in any room!,” she said.

In her proposal, Vasudevan intends to build a networking portal for females in the computing disciplines that includes undergraduates, graduates, post docs and professors. She envisions the portal becoming a Facebook application where women can communicate one-to-one.