Deming Chen

Electrical and Computer Engineering
Deming Chen
  • Electrical and Computer Engineering
410 Coordinated Science Lab MC 228
1308 W. Main St.
Urbana Illinois 61801

Primary Research Area

  • Hardware systems - Computer aided design

For more information



  • Ph.D. in Computer Science, University of California at Los Angeles, 2005
  • B.S. Computer Science, University of Pittsburgh, Pittsburgh, Pennsylvania, 1995


Dr. Deming Chen obtained his BS in computer science from University of Pittsburgh, Pennsylvania in 1995, and his MS and PhD in computer science from University of California at Los Angeles in 2001 and 2005 respectively. He worked as a software engineer between 1995-1999 and 2001-2002. He joined the ECE department of University of Illinois at Urbana-Champaign in 2005 and has been a full professor in the same department since 2015. He is a research professor in the Coordinated Science Laboratory and an affiliate professor in the CS department. His current research interests include system-level and high-level synthesis, machine learning, GPU and reconfigurable computing, computational genomics, and hardware security. He has given more than 110 invited talks sharing these research results worldwide.

Dr. Chen is a technical committee member for a series of top conferences and symposia on EDA, FPGA, low-power design, and VLSI systems design. He has also served as General or TPC Chair, Track Chair, Session Chair, Panelist, Panel Organizer, or Moderator for these conferences. Specifically, he is the General Chair for SLIP'12 and FPGA'16, the CANDE Workshop Chair in 2011, the Program Chair for PROFIT'12 and FPGA'15, the Program Co-chair for the First International Workshop on High-performance Reconfigurable Computing (H2RC), and the Program Co-chair and General Chair for GLSVLSI in 2017 and 2018, respectively. He is or has been an associated editor for IEEE TCAD, ACM TODAES, IEEE TVLSI, ACM TRETS, IEEE TCAS-I and TCAS-II, IET Cyber-Physical Systems, JCSC, and JOLPE. He obtained the Achievement Award for Excellent Teamwork from Aplus Design Technologies in 2001, the Arnold O. Beckman Research Award from UIUC in 2007, the NSF CAREER Award in 2008, and eight Best Paper Awards for ASPDAC'09, SASP'09, FCCM'11, SAAHPC'11, CODES+ISSS'13, ICCAD'15, SLIP'18, and ICCAD'18. He is included in the List of Teachers Ranked as Excellent in 2008 and 2017. He received the ACM SIGDA Outstanding New Faculty Award in 2010, and IBM Faculty Award in 2014 and 2015. In 2017 and 2019 respectively, he led a team to win the first place of DAC International System Design Contest. He has given a series of Keynote or Plenary speeches at various conferences. He is the Donald Biggar Willett Faculty Scholar of College of Engineering, an IEEE Fellow, an ACM Distinguished Speaker, and the Editor-in-Chief of ACM Transactions on Reconfigurable Technology and Systems (TRETS).

Dr. Chen was involved in several startup companies. He implemented his published algorithm on CPLD technology mapping when he was a software engineer in Aplus Design Technologies, Inc. in 2001, and the software was exclusively licensed by Altera and distributed to many customers of Altera worldwide. He is one of the inventors of the xPilot High Level Synthesis package developed at UCLA, which was licensed to AutoESL Design Technologies, Inc. Aplus was acquired by Magma in 2003, and AutoESL was acquired by Xilinx in 2011. He has also served as a consultant for several leading semiconductor companies.

In 2016, he co-founded a startup, Inspirit IoT, Inc., for design and synthesis for machine learning targeting the IoT industry. He is currently the President and Chairman of the Board of the company. Inspirit IoT recently received an NSF SBIR (Small Business Innovation Research) Award from the US government.

Professional Highlights

  • Thanos: This open-source package introduces Thanos, a fast graph partitioning tool which uses the cross-decomposition algorithm that iteratively partitions a graph. It also produces balanced loads of partitions. The algorithm is well suited for parallel GPU programming which leads to fast and high-quality graph partitioning solutions. Experimental results show that we have achieved a 30x speedup and 35% better edge cut reduction compared to the CPU version of the popular graph partitioning tool METIS on average. Download:
  • T-DLA: T-DLA (Ternarized Deep Learning Accelerator) is an open-source microprocessor designed specifically for accelerating DNN models trained with ternarized weights. This is the first instruction-based DLA design targeting ternary-quantized weights. The T-DLA system delivers up to 0.4 TOPS with 2.58 W power consumption. It is 873.6× and 5.1× faster on ImageNet for Resnet-18 model comparing to Xeon E5-2630 CPU and Nvidia 1080 Ti GPU respectively. Download:
  • DNNBuilder (Open Source): This package provides a novel solution that can automatically convert the Caffe trained DNN to the FPGA RTL level implementation without involving any hardware programming effort. It also provides uniform APIs to the users for their AI recognition task. The developers, without any FPGA programming experience, can deploy their FPGA accelerated deep learning services for both cloud and edge computing, only providing their trained Caffe model. The paper for DNNBuilder has won the IEEE/ACM William J. McCalla ICCAD Best Paper Award in 2018. Download:
  • Cloud-DNN (Open Source): A framework that maps DNN (deep neural network) models trained by Caffe to FPGAs in the cloud for inference acceleration. It takes the input *.prototxt DNN description, generates corresponding C++ network description, and then produces the final hardware accelerator IPs through high-level synthesis. The goal of Cloud-DNN is to provide more flexible and user-friendly DNN acceleration on cloud-FPGAs (e.g., AWS F1). Download:
  • RIP (Open Source): This open source project contains three inter-related software packages (fast software modeling, fast hardware modeling and design space exploration, and hardware/software co-design), for the ultimate task of automated hardware/software partitioning targeting either sophisticated SoC designs or computing on heterogeneous systems. The paper for fast hardware modeling and DSE embedded in this package has won the IEEE/ACM William J. McCalla ICCAD Best Paper Award in 2015. Download:
  • FCUDA (Open Source): A system-synthesis compiler to map GPU CUDA code to FPGA. Enable a common frontend language for heterogeneous compute platforms where FPGA and GPU co-exist. Low-power FPGA computing with comparable performance as GPU. FCUDA project has produced two Best Paper Awards for the conferences SASP'09 and FCCM'11. Download:
  • TMDFET SPICE Model (Open Source): SPICE transistor models of flexible Transition Metal Dichalcogenide Field-Effect Transistors, TMDFET. Download:
  • H.264 HLS Benchmark (Open Source): Fully synthesizable H.264 Video Decoder code, which can be synthesized into RTL with high-level synthesis for FPGA implementation and achieve real-time decoding. Download:
  • TIGER: Tiled Iterative Genome Assembler. Significant improvement over state-of-the-art de novo genome assemblers. Available since 2013. Download:
  • BLESS (Open Source): Bloom-filter-based Error Correction Solution for High throughput Sequencing Reads. Currently, the best DNA error correction tool in terms of quality and small memory usage. Available since January 2014. (More than 2000 downloads so far.) Download:
  • GNRFET HSPICE Model (Open Source): First parameterized HSPICE transistor compact models of two types of Graphene Nano-Ribbon Field-Effect Transistors, MOS-GNRFET and SB-GNRFET. Available at since July 2013. (More than 1000 downloads so far.) Download:

Research Statement

The spectacular CMOS technology scaling has created a large design productivity gap due to inherent design complexities and deep submicron issues. Development cost, including both the design cost and manufacturing cost, of integrated circuits has grown significantly given the increasing size of the design team and the lengthy design cycles. Meanwhile, intensive computational demands arising from emerging workloads, such as those in various IoT and deep-learning related domains, require new architecture and hardware designs, novel automated design flows, and efficient accelerator deployments both at the edge and in the cloud. In this context, the research group led by Prof. Chen mainly pursue the following research directions: system-level and high-level design automation, machine learning and cognitive computing, hardware/software co-design, and FPGA and GPU computing. The group recently is also pursuing several other research directions, such as computational genomics and security and computation in the smart grid.

Graduate Research Opportunities

We are recruiting. If you are passionate about research, inspired for innovation and impact, determined to pursue a Ph.D. in Computer Engineering, and your research interests match one or more topics as listed in the "RESEARCH INTERESTS" section below, please contact Prof. Chen directly through email and attach your detailed CV.

Undergraduate Research Opportunities

We are looking for committed and mature undergrad researchers for the following topics: FPGA and GPU computing, machine learning and hardware acceleration, high-level and system-level synthesis, and security in IoT and smart grid.

Research Interests

  • GPU optimization and GPU computing
  • Hardware/software co-design for SoC
  • Computational genomics
  • Machine learning and hardware acceleration
  • Reconfigurable computing and FPGAs
  • Hardware security for smart IoT applications
  • System-level and high-level synthesis

Research Areas

  • Algorithms and computational complexity
  • Computer aided design
  • Computer aided design of integrated circuits
  • Digital integrated circuits
  • Fault tolerance and reliability
  • Hardware verification and testing
  • Integrated circuit reliability
  • Logic design and VLSI
  • Nano-electronics and single electronics

Research Topics

  • Autonomous Systems and Artificial Intelligence
  • Autonomous vehicular technology, UAVs
  • Bioelectronics and Bioinformatics
  • Cognitive computing
  • Computational science and engineering
  • Cyberinfrastructures
  • Cyberphysical systems and internet of things
  • Cybersecurity and privacy
  • Data science and analytics
  • Data/Information Science and Systems
  • Distributed computing and storage systems
  • Energy
  • Genomics
  • Machine learning
  • Machine vision
  • Nanomedicine and bio-nanotechnology
  • Point-of-care diagnostics
  • Robotics
  • Smart grid and energy delivery
  • Smart infrastructures
  • Speech, language, and audio processing
  • Wearable and mobile computing

Service on College Committees

  • Representative of CSL on the College Executive Committee, 2016-2019
  • Alternate representative of CSL on the College Executive Committee, 2015-2016
  • CSL Director Search Committee, 2014

Service on Campus Committees

  • Senator, Faculty Senate, 2014-2016, 2018-2020


  • Keynote Speaker, Smart Devices Symposium, 2020
  • Keynote Speaker, Computing Conference, 2019
  • Editor-in-Chief, ACM Transactions on Reconfigurable Technology and Systems, 2019-2022
  • IEEE Fellow, 2019
  • ACM Distinguished Speaker, 2019-2022
  • First Place Winner, both the FPGA and the GPU categories, System Design Contest at IEEE/ACM Design Automation Conference, 2019
  • Best Poster Award, Joint Workshop on On-Device Machine Learning & Compact Deep Neural Network Representations (ODML-CDNNR), 2019
  • Invited Distinguished Speaker, COOL Chips, 2019
  • NSF SBIR (Small Business Innovation Research) Phase II Award, with Inspirit IoT, Inc. 2018
  • Best Paper Award, IEEE/ACM Intl Conf on Computer-Aided Design, 2018
  • Keynote Speaker, International Conference on Big Data Analytics & Data Mining, 2018
  • Best Paper Award, IEEE/ACM Intl Workshop on System-Level Interconnect Prediction, 2018
  • Plenary Speech, IEEE Computer Society Annual Symposium on VLSI, 2018
  • First Place Winner, Intl Hardware Design Contest, Design Automation Conf, 2017
  • Keynote paper, Integration, the VLSI Journal, 2017
  • Recognition of Service Award, ACM, 2016, 2018
  • Best Paper Award, IEEE/ACM Intl Conf on Computer-Aided Design, 2015
  • Keynote speech, IEEE International Conference on ASIC, 2015
  • Donald Biggar Willett Faculty Scholar, College of Engineering, University of Illinois, 2015
  • Keynote speech, IEEE International Conference on Anti-counterfeiting, Security, and Identification, 2014
  • IBM Faculty Award, 2014 and 2015
  • Best Paper Award, IEEE Intl Conf on Hardware/Software Codesign and System Synthesis, 2013
  • Best Paper Award, Symp on Application Accelerators in High Performance Computing, 2011
  • Best Paper Award, IEEE Intl Symp on Field-Programmable Custom Computing Machines, 2011
  • ACM SIGDA Outstanding New Faculty Award, 2010
  • Best Paper Award, IEEE Symp on Application Specific Processors, 2009
  • Best Paper Award, IEEE/ACM Asia and South Pacific Design Automation Conf, 2009
  • CAREER Award, National Science Foundation, 2008
  • Arnold O. Beckman Research Award, UIUC, 2007
  • Achievement Award for Excellent Teamwork, Aplus Design Technologies, Inc, 2001

Teaching Honors

  • On the List of Teachers Ranked as Excellent by Students, Spring 2008, Fall 2017

Public Service Honors

  • Founding Chair of IEEE CEDA chapter for Central Illinois (12/1/2016)

Courses Taught

  • ECE 385 - Digital Systems Laboratory
  • ECE 411 - Computer Organization & Design
  • ECE 425 - Intro to VLSI System Design
  • ECE 462 - Logic Synthesis
  • ECE 498 - IoT and Cognitive Computing
  • ECE 527 - System-On-Chip Design
  • ECE 598 - Special Topics in ECE