Janak H Patel
For More Information
- PhD - Electrical Engineering, Stanford University 1976
- MS - Electrical Engineering, Stanford University 1971
- B. Tech - Electrical Engineering, Indian Institute of Technology, Madras, India 1970
- BS - Physics, Gujarat University, India 1967
Patel’s research contributions include Pipeline Scheduling, Cache Coherence, Cache Simulation, Cache Data Prefetch, Multiprocessor memory modeling and analysis, Interconnection Networks, On-line Error Detection, Reliability analysis of memories with ECC and Scrubbing, Design for Testability, Built-In Self-Test, Fault Simulation and Automatic Test Generation. Patel is the inventor of the well known Illinois Cache Coherence Protocol and Illinois Scan Architecture, both are used heavily in most modern microprocessors. In addition, his Stride Prediction based Data Prefetch is the basis for nearly all data prefetch techniques used in most current microprocessors. Patel has supervised over 85 M.S. and Ph.D. theses and published over 200 technical papers.
During his academic stay at Illinois, Patel has had a major role in two start-ups. First was as founding technical advisor to Nexgen Microsystems, which gave rise to AMD’s present line of microprocessors. Second was as a co-founder of Sunrise Test Systems, which now is the basis for many test tools from Synopsys. In addition, Patel has provided technical consulting to a wide range of industries on architecture, reliability and testing.
He received a Bachelor of Science degree in Physics from Gujarat University, India and Bachelor of Technology in Electrical Engineering from the Indian Institute of Technology, Madras, India, and a Master of Science and Ph.D. in Electrical Engineering from Stanford University. He is a Fellow of ACM and IEEE, a recipient of the 1998 IEEE Piore Award and IEEE Test Technology Council Lifetime Achievement Award.
- Professor Emeritus ECE, U of I - January 2010 - Present
- Donald Biggar Willett Professor, College of Engineering, U of I - 1999 to August 2009
- Professor, ECE and CSL, U of I - August 1987 to August 2009
- Associate Professor, ECE and CSL, U of I - August 1983 to August 1987
- Assistant Professor, ECE and CSL, U of I - August 1981 to August 1983
- Visiting Assistant Professor, ECE and CSL, U of I - January 1980 to August 1981
- Assistant Professor, ECE, Purdue University, West Lafayette - August 1976 to December 1979
- Research Assistant, Coordinated Science Laboratory, U of I - 1974 to 1976
- Research Assistant, EE Dept., Stanford Univ., 1971-1973
Other Professional Employment
- Visiting Professor, EE Dept., Stanford Univ., CA, Sept. 2007-May 2008
- Visiting Scientist, HP Labs, Palo Alto, CA, Sept. 2007-May 2008
- Chairman, Tech. Adv. Board, Sunrise Test Systems, CA, July 1991-1998
- Vice President R & D, Sunrise Test Systems, Sunnyvale, CA, July 1990-July 1991
- Visiting Scientist, IBM Research, Yorktown Heights, NY, July 1986 - December 1986
- Visiting Scholar, Institute of Advanced Computation (NASA Project), Sunnyvale, CA - Summer 1978
- Research Assistant, Stanford Electronics Labs, Stanford University - 1972 to 1974
- Teaching Assistant, Department of Electrical Engineering, Stanford University - 1971 to 1972
Major Consulting Activities
- Sunrise Test Systems, Santa Clara, CA, 1991-1998
- Nexgen Microsystems, Sunnyvale - CA, November 1986 to 1990
- Illinois Computer Research, Inc., Champaign, IL - January 1982 to December 1987
- "Critical Operation Point" Hypothesis proposed in 2007, is making waves in the community of researchers trying to mitigate the effects of CMOS Process variations with error detection and correction methods. This work has been presented as a Distinguished Lecture at numerous Universities.
- "Illinois Scan Architecture" that I had proposed in 1998 has now been used in many modern chips from Intel, IBM and many others. It has also been incorporated in CAD tools from Cadence, Synopsis, Syntest and Magma Design.
- I first proposed in 1994 a method of non-sequential Data Pre-Fetch in general purpose microprocessors. In few years it became the basis of all Data Pre-Fetch techniques in all modern microprocessors.
- "Illinois Cache Coherence Protocol" that I had put forward in 1984 is now the basis of most multi-core microprocessors cache protocols.
- VLSI Testing and Testability, VLSI Design Automation
- Computer aided design
- Computer aided design of integrated circuits
- Computer architecture
- Digital integrated circuits
- Hardware systems
- Hardware verification and testing
- Logic design and VLSI
Chapters in Books
- A. N. Choudhary, J. H. Patel, and N. Ahuja, "Architecture and performance evaluation of NETRA," Chapter in Parallel Architectures and Algorithms for Image Understanding, edited by V. K. Prasanna Kumar, Academic Press, New York, NY, pp. 251-279, July, 1991.
- R. K. Iyer, J. H. Patel, W. K. Fuchs, P. Banerjee, and R. Horst, "Hardware and Software Fault-Tolerance," chapter in Encyclopedia of Microcomputers, vol. 8, pp. 161-200, 1991.
- M. Sharma, N. Ahuja, and J. H. Patel, "NETRA: An architecture for a large scale multiprocessor vision system," in Parallel Computer Vision, Leonard Uhr, Editor, Academic Press: Orlando, Florida, pp. 87-107, 1987.
- J. A. Abraham, G. Metze, R. K. Iyer and J. H. Patel, "The evolution of fault-tolerant computing at the University of Illinois," in The Evolution of Fault-Tolerant Computing, Springer-Verlag, pp. 271-288, 1987.
- F. A. Briggs, K. S. Fu, K. Hwang, and J. H. Patel, "A shared resource multiple microprocessor system for pattern recognition and image processing," in Special Computer Architecture for Pattern Processing, K. S. Fu and T. Ichikawa Eds., CRC PRESS, 1980; Boca Raton, Florida, Pp. 221-238, 1982.
- Software: HITEC and PROOFS Software for Automatic Test Generation and Fault Simulation Distributed to: Industry (AT&T, Motorola, HP, Intel, NEC, AMD, Mitre), Universities (CMU, Austin, Texas, Virginia, Iowa, Yale, Texas A&M) and licensed by the University to the Sunrise Test Systems.
- Patents: U.S. Patent No. 5,377,197, Issue Date: December 27, 1994, "Method for automatically generating test vectors for digital integrated circuits," Inventors: T. M. Niermann and J. H. Patel.
Other Scholarly Activities
- Program Chair, 1994 Int. Symp. on Computer Architecture, Chicago, Illinois
- Chair, Organizing Committee, 1989 Int. Symp. on Fault-Tolerant Computing, Chicago, Illinois
- IEEE Test Technology Council Lifetime Achievement Award, 2016
- Fellow, ACM, 2001
- IEEE Emanuel R. Piore Award, 1998
- Best Paper Award, 1998 IEEE VLSI Test Symposium
- Associate, Center for Advanced Study, 1992-93
- Fellow, IEEE, 1989
- Distinguished Lecture, Texas A&M Univ., College Station, TX, 2009
- Distinguished Lecture, Georgia Tech, Atlanta, GA, 2009
- Distinguished Lecture, North Western University, Evanston, IL, 2009
- Keynote Speaker, IEEE International Test Conference, Austin, TX, 2006
- Distinguished Lecture, Electrical and Computer Engineering, Purdue University, 2001
- Nomination for Best Paper Award, ACM/IEEE Design Automation Conf. 1994
- MCM Packaging Distinguished Lecture, Georgia Tech, Atlanta, GA, 1994
- Inaugurated the Distinguished Lecture Series on Electronic Design Automation at IBM, Endicott, NY, 1993
- Analog Devices Distinguished Lecture, Univ. of Michigan, Ann Arbor, 1992
- Nomination for Best Paper Award, ACM/IEEE Design Automation Conf. 1987 (simulation and Test Category)
- Keynote Speaker 1985 AT&T Technologies Conference on Electronic Testing, April 1985
Recent Courses Taught
- ECE 462 - Logic Synthesis