IEEE Micro selects bespoke processor paper as "top pick"
Joseph Park, ECE ILLINOIS
1/16/2018 3:22:25 PM
A paper by ECE ILLINOIS Associate Professor Rakesh Kumar
and graduate students Henry John Duwe, III
and Weidong Ye
has been named as an IEEE Micro Top Pick Paper for 2017. Kumar and his students are also affiliated with the Coordinated Science Lab at Illinois. Collaborating with Hari Cherupalli and John Sartori from the University of Minnesota, their paper "Bespoke Processors for Applications with Ultra-low Area and Power Constraints" has been recongized as one of the 12 best published in computer architecture conferences this past year, based on its novelty and potential for long-term impact.
Kumar and his associates make a case for "bespoke processor design, an automated approach that tailors a general purpose processor IP to a target application by removing all gates from the design that can never be used by the application." Since removed gates are not used by an application, bespoke processors have the potential to achieve significantly lower area and power without degrading in performance. Furthermore, gate removal can "expose additional timing slack that can be exploited to increase area and power savings or performance of a bespoke design." The bespoke processor design reduces area and power by 62% and 50%, on average respectively, and exploiting the exposed timing slack improves average power savings to 65%.
With the concurrent emergence of implantables, wearables, printed electronics, and IoT (Internet of Things) which all rely on ultra-low-power general purpose microcontrollers and microprocessors, the application of bespoke processors could save a significant amount of space and power.
Read the full paper and look for its inclusion in the May/June 2018 issue of IEEE Micro magazine.