Bayram and team improves GaN-on-Silicon technology by optimizing layers' composition

A team of University of Illinois researchers has recently advanced gallium nitride (GaN)-on-silicon transistor technology by optimizing the composition of the semiconductor layers that make up the device. Working with industry partners Veeco and IBM, the team created the high electron mobility transistor (HEMT) structure on a 200 mm silicon substrate with a process that will scale to larger industry-standard wafer sizes.

According to ECE Assistant Professor Can Bayram, his team created the GaN HEMT structure on a silicon platform because it’s compatible with existing CMOS manufacturing processes and it’s less expensive than other substrate options like sapphire and silicon carbide.

However, silicon does have its challenges. Namely, the lattice constant, or space between silicon atoms, doesn’t match up with the atomic structure of the GaN grown on top of it. “When you grow the GaN on top, there’s a lot of strain between the layers, so we grew buffer layers [between the silicon and GaN] to help change the lattice constant into the proper size,” explained ECE undergraduate lead researcher Josh Perozek.

Without these buffer layers, cracks or other defects will form in the GaN material, which would prevent the transistor from operating properly. Specifically, these defects—threading dislocations or holes where atoms should be—ruin the properties of the 2-dimensional electron gas channel in the device. This channel is critical to the HEMTs ability to conduct current and function at high frequencies.

“The single most important thing for these GaN [HEMT] devices is to have high 2D electron gas concentration,” said Bayram, about the accumulation of electrons in a channel at the interface between the silicon and the various GaN-based layers above it. “The problem is you have to control the strain balance among all those layers—from substrate all the way up to the channel—so as to maximize the density of the of the conducting electrons in order to get the fastest transistor with the highest possible power density.”

After studying three different buffer layer configurations, Bayram’s team discovered that thicker buffer layers made of graded AlGaN reduce threading dislocation, and stacking those layers reduces stress. With this type of configuration, the team achieved an electron mobility of 1,800 cm²/V-sec. “The less strain there is on the GaN layer, the higher the mobility will be, which ultimately corresponds to higher transistor operating frequencies,” said Hsuan-Ping Lee, an ECE graduate student researcher leading the scaling of these devices for 5G applications.

According to Bayram, the next step for his team is to fabricate fully functional high-frequency GaN HEMTs on a silicon platform for use in the 5G wireless data networks.

When it’s fully deployed, the 5G network will enable faster data rates for the world’s 8 billion mobile phones, and will provide better connectivity and performance for Internet of Things (IoT) devices and driverless cars.

The team, in collaboration with Veeco and IBM, conducted their research at the University of Illinois Micro + Nanotechnology Lab with support from the Air Force Office of Scientific Research. Their work can be found at J. Phys. D Appl. Phys. 50 (2017) 055103. The orginal story can be found here.