Two ECE Engineers honored with Best Artifact Award at top conference

11/24/2025 Jeni Bushman, Edited by Megan Altmyer

Yuqi Xue, an ECE doctoral candidate, and ECE Associate Professor Jian Huang were recently presented with the Best Artifact Award at the 58th annual IEEE/ACM International Symposium on Microarchitecture (MICRO) held in Seoul, South Korea.

Written by Jeni Bushman, Edited by Megan Altmyer

A duo of researchers from the Department of Electrical and Computer Engineering at The Grainger College of Engineering, University of Illinois Urbana-Champaign, have been recognized by MICRO for their work on energy efficiency in neural processing units (NPU). Yuqi Xue, a doctoral candidate in ECE, and Jian Huang, ECE associate professor, were presented with the Best Artifact Award at the 58th annual IEEE/ACM International Symposium on Microarchitecture (MICRO) held in Seoul, South Korea.

Best Artifact Award certificate image for 2025Xue and Huang were recognized for their work on power-gating, a technique that reduces power consumption in AI chips by disabling the power supply to unused portions. The ECE engineers used this technique to develop ReGate, an approach that enables fine-grained power-gating of individual hardware components in NPU chips.

“The core idea of this project is that we are the first to systematically enable power gating across all major components in NPU chips,” Xue said. “We did a study on Google’s tensor processing unit (TPU) chip and found that a significant portion of power is consumed just to keep the hardware “awake” – what we call static power. It’s like an employee idling in an office, waiting for a task: not every component on the chip will be fully utilized at any given time, but they are still consuming power.”

The researchers addressed this problem by using compiler analysis to identify a chip’s underutilized components and put them in sleep mode, significantly reducing the chip’s power consumption. Their method represents an important contribution towards global data center sustainability.

“NPU chips are the backbone of today’s AI data centers, and power-gating can significantly reduce their power consumption,” Huang said.

Now in its 58th year, MICRO is a premier opportunity for members of both industry and academia to explore innovations in computer architecture and hardware design. Xue attributes his team’s recognition to their user-friendly source code, which features automated scripts and thorough documentation that allow users to extend the codebase for their own research.

“Illinois has a prominent culture of hardware and architecture research, which we strongly encourage to be open source,” Huang said. “ReGate is a good example of this. We encourage everyone — especially the students who are interested in hardware systems — to join our efforts in conducting open-source hardware research.”

The study, “ReGate: Enabling Power Gating in Neural Processing Units,” is available online. DOI: 10.1145/3725843.3756038


Illinois Grainger Engineering Affiliations

Jian Huang is an Illinois Grainger Engineering associate professor of electrical and computer engineering in the Department of Electrical and Computer Engineering. He is affiliated with the Coordinated Science Laboratory, Information Trust Institute, and the Siebel School of Computing and Data Science.


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This story was published November 24, 2025.