ECE 444

• Microelectronics and Photonics

Preview ECE 444

The goal of this course is to give advanced undergraduates and beginning graduate students a thorough understanding of the process technology underlying modern integrated circuits. This course provides direct hands-on exposure to many aspects of processing technology, experience in the design of semiconductor device processes, and a clear understanding of the economic and technical trade-offs inherent in the industry.

• Introduction
• Process integration
• Cleanrooms and wafer cleaning
• Silicon wafer
• Oxidation
• Photolithography
• Etching processes
• Chemical mechanical planarization
• Junction diffusion
• Diffusion technology
• Chemical vapor deposition
• Physical vapor deposition
• Ion implantation
• Back end of line processes

The goal of this course is to give advanced undergraduates and beginning graduate students a thorough understanding of the process technology underlying modern integrated circuits. This course provides direct hands-on exposure to many aspects of processing technology, experience in the design of semiconductor device processes, and a clear understanding of the economic and technical trade-offs inherent in the industry.

Topics:

• Introduction
• Process integration
• Cleanrooms and wafer cleaning
• Silicon wafer
• Oxidation
• Photolithography
• Etching processes
• Chemical mechanical planarization
• Junction diffusion
• Diffusion technology
• Chemical vapor deposition
• Physical vapor deposition
• Ion implantation
• Back end of line processes

Clarius software for device testing. Math and plotting software for analysis of device characteristics. Use of references at http://fabweb.ece.illinois.edu/. Mask design using KLayout.

• Semiconductor physics
• The p-n junction
• The bipolar junction transistor
• The metal oxide semiconductor (MOS) field-effect transistor

Plummer, James D., and Peter B. Griffin. Integrated Circuit Fabrication: Science and Technology. Cambridge University Press, 2023.

G. E. Anner, Planar Processing Primer.

Engineering Science: 3 credits
Engineering Design: 1 credit

This is a senior elective laboratory course for electrical engineering and computer engineering majors. Students from other departments are also welcome, particularly those in Materials Science and Engineering, Mechanical Engineering, Chemical Engineering, Nuclear, Plasma, and Radiological Engineering, and Physics. Graduate credit is available. The goals of this course are to provide a detailed understanding and hands-on laboratory experience in the wide range of technical processes that comprise modern integrated circuits. The course is intended to (a) be the primary core course for students seeking to pursue a career in integrated circuit fabrication, and (b) provide detailed background material for students interested in other aspects of the semiconductor industry, such as VLSI design or microprocessor architecture.

By the time of Exam 1 (or after 8 lectures) the students should be able to do the following:

1. Draw the cross-section and identify the final device that results from a given IC mask set and vice versa. (1, 2)
2. Explain Moore's Law and technology nodes (2)
3. Describe the self-aligned gate process and the problem it solved. (2)
4. Use principles of semiconductor device physics to explain the Boltzmann limit for transistors, MOSFET transfer characteristics, subthreshold swing, the end of Dennard scaling, the introduction of high-K gate dielectrics, strain engineering, and the evolution from planar MOSFETs to finFETs to gate-all-around FETs (1, 2, 6)
5. Outline and describe the unit processes and a modern process flow for fabricating planar CMOS ICs. (2)

By the time of Exam 2 (or after 14 lectures) the students should be able to do the following:

1. Explain the process for manufacturing silicon wafers, dopant/impurity incorporation, and methods for controlling point and extended defects. (1, 6)
2. Calculate the impurity doping density of a silicon wafer or epitaxial layer from four point probe measurements of the sheet resistance. (1)
3. Explain the importance of cleanrooms, automated wafer handling, and wet cleaning in semiconductor manufacturing and yield (2)

By the time of Exam 3 (or after 22 lectures) the students should be able to do the following:

1. Derive Fick’s Laws for diffusion and explain the significance of the exponential form of the diffusion coefficient. (1)
2. Understand and explain Grove’s model for oxidation, including the boundary layer, mass transfer coefficient, diffusion through an existing oxide layer, and reaction at the Si-SiO2 interface. (1)
3. Design the process for a desired total oxide thickness using a combination of multiple dry or wet oxidation process steps. (2)
4. Understand characterization of SiO2, including optical methods, capacitance-voltage measurements, electrical identification of traps, and methods for trap mitigation (1)
5. Understand the chemistry of photoresists (PRs), explain the differences between positive and negative PR, describe chemically amplified resists, describe the chemistry of PR developer, and PR stripping. (2)
6. Describe the complete optical system of contact, proximity, and step-and-repeat projection aligners, including pros and cons for each. (2)
7. Describe the Rayleigh limit and the effect of exposure wavelength on resolution, numerical aperture, depth of focus, and modulation transfer function (1)
8. Describe diffraction effects, the connection between the spatial Fourier transform and the far-field pattern, resolution enhancement techniques, and methods to go beyond the Rayleigh limit (2)

By the time of Exam 4 (or after 28 lectures) the students should be able to do the following:

1. Understand the chemical process for wet chemical etching and design a process to obtain a specific etch rate and profile. (2)
2. Define isotropic and anisotropic etching and calculate the effects of undercutting on minimum linewidth systems. (1)
3. Describe plasma, the roles of radicals and ions in dry etching, and how they can be used to form high aspect-ratio structures (1)
4. Apply the concepts of sticking coefficient and cosine law to dry etching. (1)
5. Describe common problems in dry etching and potential mitigations (2)
6. Understand the implications of the binary phase diagrams of important elements and silicon, demonstrate the ability to calculate liquid and solid distributions by the lever rule, define solid solubility. (2)
7. Apply Fick’s Laws to the thermal diffusion of impurities into silicon for both finite and infinite sources. (1)
8. Design the process time, species, and temperature for a desired pn junction diode cross section. (2)
9. Describe vacancy- and interstitial-assisted diffusion. (1)

By the time of Exam 5 (or after 35 lectures) the students should be able to do the following:

1. Describe resistivity, sheet resistance, and specific contact resistance and methods to measure them. (1)
2. Understand the process flow for the formation of a diffused bipolar junction transistor. (2)
3. Design the diffusion parameters for a desired bipolar junction transistor working from the required diffused layer sheet resistances. (2)
4. Describe the mechanisms involved with ion implantation and calculate junction depths for typical implant conditions. (1)
5. Describe amorphization, channeling, and masking in ion implantation (2)
6. Outline the advantages and disadvantages of various methods for removing the damage introduced by ion implantation. (1)
7. Describe the importance of complex dopant profiles in controlling MOSFET electrostatics and parasitics. (1)

By the time of Exam 6 (or after 43 lectures) the students should be able to do the following:

1. Explain the process of chemical vapor deposition and Si epitaxial growth. (1)
2. Differentiate between reaction rate- and mass transport-limited growth, and state pros and cons of hot-wall, cold-wall, and single-wafer reactor designs. (1)
3. Explain the process of atomic layer deposition. (1)
4. Explain the mechanisms and pros and cons of vacuum evaporation and sputtering. (1)
5. Describe back-end-of-line (BEOL) processing and chemomechanical polishing (CMP). (2)
6. Describe methods for controlling RC delays in the BEOL, introduction of low-K interlayer dielectric, and challenges of Cu metallization, including the need for barrier layers, adhesion layers, and dual-damascene processing. (2)
7. Describe basic packaging methods, including wire bonding and bump bonding. (2)
8. Outline the salient features of statistical process control and metrology, and show the relationship to modern IC fabrication yield. (1)
9. Describe how and why modern IC process technology and device structures differ from what is made in ECE 444 lab. (1)
10. Explain advanced IC processes not covered in class. (1), (3), (4), (7)

By the time of the Final Exam (after 43 lectures) the students should be able to do the following:

1. Fabricate a selection of IC devices, including diodes, diffused capacitors, Schottky diodes, pn junction diodes, npn bipolar transistors, p-MOS transistors, n-MOS transistors, CMOS devices, and ring oscillators. (5), (6)
2. Understand and prove the limits of key process parameters including wet etch undercutting, minimum linewidth lithography, oxidation growth rates, and metalization coverage. (6)
3. Use a probe station and semiconductor parameter analyzer to test and characterize the devices fabricated, and apply statistical criteria to provide upper and lower limits to process sensitivity. (6), (5)