ECE 427

https://courses.grainger.illinois.edu/ECE427/fa2025/

ECE 427 spans two semesters in total, GDS files are sent to foundry for tapeout at the end of the first semester. In the second semester, students signup for an independent study course to test and bringup their chips when it returns from foundry. Instructor approval is required for all projects.

To work in teams to design, verify, validate, tapeout a chip on TSMC 65nm technology.

• VLSI Design and Integration
• Digital and Analog IC Design
• Computer Architecture
• Hardware Verification
• Hardware Synthesis
• Design for Test
• IC Validation

Detailed Overview – ECE 427 will allow students with a hardware focus to culminate knowledge from computer architecture (ECE 411), digital design (ECE 385), analog and digital IC design (ECE 482/483), and layout (ECE 425) into a complex year-long project to design and fabricate a chip. Students will work in teams of 4-6 in a startup-like fashion, each member having well-defined roles based on project needs. In the first semester, each team will propose a design in the form of specifications, write a Verilog/SystemVerilog/Chisel, synthesizable C++ (HLS), or equivalent model of the chip and its components, design schematics, create a testing/debug strategy, and perform layout, integration, and verification of the chip before taping it out. In the second semester, students will take an individual study course when the chips return from the foundry to bringup and test their chips. Roughly nine to eleven hours of lab work is expected per week. Overall, this course will require a time commitment of 13-15 hours per week per student.

Project Timeline – Due to time constraints of the semester, each team will be following a very tight schedule to complete all design steps from architecture to design to implementation. Students will need to form groups one semester before taking ECE 427. All groups will do a project proposal presentation in the first week of the class. The first 4-6 weeks of coursework are allocated to RTL design and verification. By week 8, students should submit a mid-term progress report that details their completed design in the first half of the semester. For the remainder of the semester, students will perform physical design and implementation, with final GDS files to be submitted in mid-December. A complete timeline is shown on the next page.

Progress Meetings and Industry Mentors – Members of each group are expected to meet with either the instructor or TA(s) at least once each week (all members attending if possible). Additionally, each group may be assigned an industry mentor who will check on their progress on a bi-weekly basis. Towards the end of the semester, students will need to be in contact with engineers of an MPW company to guide them through the final tapeout process.

Students will work in specialized EDA VMs reserved for ECE 427. All students must sign an NDA with the foundry to access PDKs.

Access to advanced FPGA boards (Xilinx Virtex Ultrascale+), soldering machines, and other necessary equipment will be provided.

• Synopsys Design Compiler
• Synopsys VCS
• Cadence Innovus
• Cadence Virtuoso
• Siemens Calibre

Prior experience in IC (digital / analog) design and layout is required. Depending on project needs, domain-specific knowledge in computer architecture, circuits, memories, etc. may also be prerequisite.

D. Harris and N. Weste, CMOS VLSI Design : A Circuits and Systems Perspective.

Students may refer to past projects: https://courses.grainger.illinois.edu/ECE498HK/fa2024/projects.html.

This senior-level course immerses students in the fast-paced world of chip design, challenging them to design and tapeout an integrated circuit on a commercial process node within a single semester. Not only are students challenged from a design complexity standpoint, this course also provides a valuable experience in teamwork and project management, putting them in a work environment closer to a startup than a classroom. Throughout the semester, staff and industry mentors will guide students as they navigate through design problems, teamwork challenges, and plan for tight foundry deadlines. Ultimately, this course provides students with practical, in-demand skills, preparing them for future industry positions in the areas of computer architecture, digital and analog IC design, verification and validation, and silicon engineering in general.

By the end of the semester, we expect students to be able to do the following.

• Understand the overall ASIC design flow from high-level architecture conceptualization to final chip tapeout. (1)
• Research background knowledge and prior works based on your project's domain, and introduce innovations that address shortcomings of state-of-the-art designs. (7)
• Write synthesizable Verilog/SV for a complex hardware design; write assertions and testbenches based on design needs. (1), (2)
• Analyze bottlenecks in your chip's performance based on simulation results or FPGA prototyping, and improve your chip's design by eliminating or mitigating these bottlenecks. (6)
• Analyze potential faults and points of failure in your chip to formulate a debug and design for test (DFT) strategy for bringup. (6)
• Use commercial EDA synthesis tools (e.g., Synopsys Design Compiler) to set timing constraints, synthesize a design, and apply automated DFT methods for scan insertion. (2)
• Use commercial EDA implementation tools (e.g., Cadence Innovus / Virtuoso) to:
  1. Perform physical implementation (floorplanning, clock tree synthesis, place and route, timing analysis, etc.). (2)
  2. Perform physical validation and signoff. (2)
• Work in a team following a tight tapeout schedule, communicate with industry mentors and foundry partners. (4), (5)
• Write a conference-level research paper detailing the design choices, novelty, performance analysis of your chip. (3)