ECE 385 - Digital Systems Laboratory

Semesters Offered

TitleRubricSectionCRNTypeHoursTimesDaysLocationInstructor
Digital Systems LaboratoryECE385AB136843LAB00800 - 1050 F  4072 ECE Building 
Digital Systems LaboratoryECE385AB236856LAB01500 - 1750 F  4072 ECE Building 
Digital Systems LaboratoryECE385AB336821LAB01400 - 1650 R  4072 ECE Building 
Digital Systems LaboratoryECE385AB436823LAB00800 - 1050 R  4072 ECE Building 
Digital Systems LaboratoryECE385AB536826LAB01100 - 1350 R  4072 ECE Building 
Digital Systems LaboratoryECE385AB636835LAB01200 - 1450 W  4072 ECE Building 
Digital Systems LaboratoryECE385AB736829LAB01100 - 1350 F  4072 ECE Building 
Digital Systems LaboratoryECE385AB836838LAB00900 - 1150 W  4072 ECE Building 
Digital Systems LaboratoryECE385ABC36773LAB01400 - 1650 T  4072 ECE Building 
Digital Systems LaboratoryECE385ABD36803LAB00800 - 1050 T  4072 ECE Building 
Digital Systems LaboratoryECE385ABE36805LAB01100 - 1350 T  4072 ECE Building 
Digital Systems LaboratoryECE385AL136720LEC31600 - 1650 M W  1002 ECE Building Zuofu Cheng

Official Description

Design, build, and test digital systems using transistor-transistor logic (TTL), SystemVerilog, and field-programmable gate arrays (FPGAs). Topics include combinational and sequential logic, storage elements, input/output and display, timing analysis, design tradeoffs, synchronous and asynchronous design methods, datapath and controller, microprocessor design, software/hardware co-design, and system-on-a-chip. Course Information: Prerequisite: ECE 110 and ECE 220. Class Schedule Information: Students must register for one lab and one lecture section.

Subject Area

Computer Engineering

Course Director

Description

Introduction to the experimental analysis and synthesis of digital networks, including the use of a microcomputer as a controller.

Goals

This course is designed to give students in computer and electrical engineering an ability to design, build, and debug digital systems that include microprocessors, memory systems, and peripherals.

Topics

  • Combinational logic circuits
  • Storage elements
  • Hazards and race conditions
  • Circuit characteristics (fanout, delays, etc.)
  • Field Programmable Gate Arrays (FPGAs)
  • Combinational networks (adders, multiplexes, etc.) in SystemVerilog
  • Sequential networks (counters, shift registers, etc.) in SystemVerilog
  • Synchronous state machines
  • Static timing analysis, clock domains, metastability, and synchronization
  • Logic simulation and testbenches
  • Microprocessors and system on chip
  • Project using a microprocessor and system on chip concepts

Detailed Description and Outline

This course is designed to give students in computer and electrical engineering an ability to design, build, and debug digital systems that include microprocessors, memory systems, and peripherals.

Topics:

  • Combinational logic circuits
  • Storage elements
  • Hazards and race conditions
  • Circuit characteristics (fanout, delays, etc.)
  • Field Programmable Gate Arrays (FPGAs)
  • Combinational networks (adders, multiplexes, etc.) in SystemVerilog
  • Sequential networks (counters, shift registers, etc.) in SystemVerilog
  • Synchronous state machines
  • Static timing analysis, clock domains, metastability, and synchronization
  • Microprocessors and system on chip
  • Project using a microprocessor and system on chip concepts

Computer Usage

At different times during the term students may use a IBM compatible personal computer and the appropriate software tools to design and simulate digital circuits. During the last 5 weeks the students use a microcomputer development system to program, debug, and if necessary, emulate a microprocessor-based project. 1. Nine experiments of increasing complexity covering first 10 topics. Groups of 2 students use a protoboard to build their circuits and an I/O lab station, oscilloscope, logic analyzer, and pulse generator to debug and demonstrate their experiments. Programmable Logic Devies may be used in some experiments. 2. During the last 5 weeks, groups of 2 students choose, design, build, and debug some hardware to be controlled by a microcomputer programmed by them using the microcomputer development system.

Topical Prerequisites

  • Basic electronics laboratory experience
  • Ability to use oscilloscopes
  • Ability to design combinational and sequential circuits
  • An understanding of basic computer organization
  • Ability to program in the C programming language

Texts

Class Notes

ABET Category

Engineering Science: 10%
Engineering Design: 90%

Course Goals

The course is required for both electrical and computer engineering students. The course is designed to give students in computer and electrical engineering ability to design, build, and debug digital systems. The first half of the course uses standard TTL chips, wires and a proto board. The second half of the course uses CAD tools to synthesize logic described in SystemVerilog, which is then mapped to an FPGA.

Instructional Objectives

A. At the end of the first week (Experiment #1), the students should be able to do the following:

1. Design, document, and build a logic circuit to eliminate the problems caused by “contact bounce” in a mechanical switch. (a, b, c)

2. Detect and identify static hazards (glitches) in a logic circuit caused by delays in logic gates. (a, b)

3. Design, document, and build additional logic circuitry to eliminate glitches in existing logic circuits. (a, b, c, e, k)

4. Design, document, and build an input/output logic circuit with four ‘debounced’ switches and six LED’s (Light Emitting Diodes). (b, c, k)

B. At the end of the second week (Experiment #2), the students should be able to do the following:

1. Identify different types of digital storage elements (latches and flip-flops) and draw the corresponding timing diagrams. (b, k)

2. Design, build, and test a flip-flop with a new given behavior, using logic gates. (a, b, c, e, k)

3. Devise and perform tests to determine set-up and hold times in a given flip-flop. (b, k)

C. At the end of the third week (Experiment #3), the students should be able to do the following:

1. Design, build, and test a logic circuit which behaves as a 4-bit serial logic processor (a, b, c, e, k)

2. Build, test, and possibly improve a provided state machine specification (b, c, k)

3. Document the entirety of the logic design in a correct, coherent, and complete manner (g)

D. At the end of the fourth week (Experiment #4), the students should be able to do the following:

1. Learn, configure, and operate commercial Electronic Design Automation (EDA) tools (i)

2. Design, document, acarry ripple adder, carry lookahead adder, and carry select adder in SystemVerilog. (b, c, k)

3. Implement and test the design on a FPGA evaluation board (a, b, c, e, g, k, i)

E. At the end of the fifth week (experiment #5), the students should be able to do the following:

1. Design, document, and build, and test a 8-bit by 8-bit multiplier using SystemVerilog (a, b, c, e, g, k)

F. At the end of the sixth week (Experiment #6), the students should be able to do the following:

1. Design, document, and build a datapath for an SLC3 (Simplified LC-3) microprocessor (a, b, c, e, g, k)

G. At the end of the seventh week (Experiment #6 part 2), the students should be able to do the following:

1. Design, document, and build, and test a complete SLC-3 microprocessor on the FPGA using provided C language programs (a, b, c, e, g, k, i)

H. At the end of the eighth week (Experiment #7), the students should be able to do the following:

1. Design, document, and build a system-on-chip (SoC) platform using the FPGA development board (a, b, c, e, g, k, i)

I. At the end of the ninth week (Experiment #8), the students should be able to do the following:

1. Design, document, and test a USB keyboard protocol and a standard VGA protocol using SystemVerilog and FPGA. (a, b, c, e, g, k, i)

J. At the end of the eleventh week (Experiment #9), the students should be able to do the following:

1. Design, document, and build an AES encryption software module running on the CPU side of the SoC platform. (a, b, c, e, g, k, i)

2. Design, document, and build an AES decryption accelerator module to accelerate AES operations using the FPGA (a, b, c, e, g, k, i)

K. At the end of the fourteenth week (Four Weeks Final Project), the students should be able to do the following:

1. Propose, design, document, and build a digital system that is challenging and does something interesting. SystemVerilog and FPGA are used in conjunction with A/D and D/A converters, LCD display panels, keyboards, joy sticks, speakers, cameras, and VGA monitors. (a, b, c, d, e, g, k, i)

Last updated

10/19/2018by Zuofu Cheng