Jose E Schutt-Aine

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Education

• PhD Electrical & Computer Engineering University of Illinois May 1988

Research Statement

The era of big data will lead to systems necessitating the transport of large amounts of information. Today's high-speed I/O signaling links are faced with difficult challenges: pins and interconnects available for off-chip signaling remain almost constant, while the throughput needed is increasing and the required aggregate bandwidths are moving into the Tb/s range (with target bit error rates as low as 10-21 for memory links).

High-speed chip-to-chip communication has historically been considered less critical than the on-chip signaling performance; however, due to today's huge demands for data throughput, off-chip interconnect bandwidth is increasingly becoming the system bottleneck, and creative solutions are needed to meet the requirements, now measured even in terabytes per second for graphic processing cores. Due to manufacturing and technology limitations, the physical dimension scaling of the passive package and interconnect systems is unable to keep up with the rapid miniaturization benefits enjoyed by active devices (such as silicon chips in CMOS technology nodes) which is dictated by Moore's law. Therefore, the resources (pins and interconnects) available for off-chip signaling remain almost constant, while the throughput needed is increasing. This trend is expected to persist in the future. At the same time, in order to keep up with the data throughput needed over limited resources, high edge rates are being used for signaling. This causes various signal integrity impairments, which in turn limit the system performance and force the data rates to be well below the Shannon limit of the channel capacity. Coupled with the limited channel resources are the conflicting requirements of low power and extremely reliable signaling . All of these limitations combined call for creative solutions in order to keep up with the performance demands of next-generation systems.

In our research group we investigate how these changes will affect the different aspects of high-speed link design. We develop modeling and simulation strategies as well as techniques for mitigating noise while reducing power.

Research Interests

• Machine Learning for High-Speed System Modeling
• Signal Integrity
• CAD Tools for Interconnects and Packages
• High-Performance Computing for Electromagnetic Modeling
• X-Parameter Modeling and Simulation
• High-Frequency Measurements
• Mixed-Signal Design

Research Topics

• Electronic Design Automation

Articles in Conference Proceedings

• Xu Chen, Michael Qiu, José E. Schutt-Ainé, and Andreas C. Cangellaris, "Stochastic LIM for Transient Simulation of Circuits with Uncertainties", Proceedings of the 23rd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 29-32, Portland, OR, October 2014.
• Xiaoyan Y.Z. Xiong, Li Jun Jiang, Jose E. Schutt-Aine and Weng Cho Chew, "Blackbox Macro-modeling of the Nonlinearity Based on Volterra Series Representation of X-Parameters", Proceedings of the 23rd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 85-88, Portland, OR, October 2014.
• Jose Schutt-Aine, Robust SPICE circuit generation using scattering parameters", Proceedings of the 2014 IEEE International Symposium on Electromagnetic Compatibility (EMC), pp. 230-233, Rayleigh, NC August 2014.
• Tong Zhang ; Xu Chen ; Schutt-Aine, J.E. ; Cangellaris, A.C., "Statistical analysis of fiber weave effect over differential microstrips on printed circuit boards", Proceedings of the 2014 IEEE 18th Workshop on Signal and Power Integrity (SPI), pp. 1-4, Ghent, Belgium, May 2014.
• T. M. Comberiate, J. E. Schutt-Aine, "Using X-parameters to generate IBIS models Signal and Power Integrity”, Proceedings of the 17th IEEE Workshop on Signal and Power Integrity (SPI-2013), Paris, May 2013.

Professional Societies

• ABET Program Evaluator
• Editor in Chief, IEEE Transactions on Advanced Packaging, 2007-present

Service on Campus Committees

• Graduate College Fellowship Committee 2013-Present

Honors

• Best Paper Award IEEE-EPEPS-2014
• College of Engineering 2014 Outstanding Advisors List
• Best Paper Award IEEE-EDAPS-2013
• Best Student Paper Award IEEE-EPEPS-2013
• Best Poster Paper Award IEEE-EPEPS-2011
• Certificate of Achievement DesignCon 2011 Paper Award Finalist
• IEEE Fellow 2007, for contributions to modeling and simulation of distributed circuits with applications to signal integrity
• Certificate of Honor, IEEE CPMT, Bangalore Chapter, India, December 2005
• 2000 UIUC-NCSA Faculty Fellow
• 1998 CPMT-IEEE Education Award
• NSF MCAA Award, 1996
• 1994 Advisor's List for Advising Excellence, Spring 1994
• NASA Faculty Award for Research, 1992
• NSF MRI Award, 1991

Teaching Honors

• CPMT-IEEE Education Award (1998 )
• 1994 Advisor's List for advising excellence (Spring 1994)
• Incomplete List of Teachers Ranked as Excellent by their Students (Spring 1988, Fall 1988)