Kumar's research indicates hidden potential of waferscale chip
ECE ILLINOIS Associate Professor Rakesh Kumar is leading a team of researchers from the University of Illinois Urbana-Champaign and the University of California, Los Angeles to develop waferscale processor using a new wafer-level interconnect technology that could outperform an equivalent multi-chip module MCM and deliver energy more efficiently.
Using Silicon Interconnect Fabric or Si-IF, the researchers's work offered improved bandwith, latency, and energy efficiency than package-level interconnects. According to The Next Platform, "the Si-IF base material is integrated with copper pillar I/O pins and inter-die links," essentially replacing the PCB with a silicon substrate and wlloing for the dies be bonded directly to the wafer.
The concept of waferscale integration (WSI) focuses on how a wafer can serve as the substrate for a "super-chip," with "individual components wire together in place." In theory, this modification could cut costs and improve performance. Furthermore, this allows for much denser devices to be constructed with less than 10% of the area occupied by interconnects.
Another key advantage of WSI is that each multi-GPU wafer would appear as a single super-sized GPU to software. Despite even modest performance and energy advantages, the increase in programmer productivity would make this technology appealing to developers.
Kumar is also affiliated with the CSL.