Kumar's silicon waferscale approach competes with biggest chip ever built
Joseph Park, ECE ILLINOIS
9/26/2019 3:02:22 PM
ECE ILLINOIS Professor Rakesh Kumar
and a team of researchers from the University of Illinois at Urbana-Champaign and the University of California, Los Angeles are working together to develop silicon interconnect fabric.
Silicon Interconnection Fabric allows for dielets to "sit as close as 100 micrometers" away from each other, "allowing for interchip communication" that resembles the characteristics of a single chip according to an article by IEEE Spectrum.
Photo: Cerebras Systems
Cerebras, a startup dedicated to accelerating deep learning, recently revealed a new chip at the IEEE Hot Chips symposium at Stanford University. Known as the Cerebras Wafer-Scale Engine (WSE), this chip is considered to be the largest chip ever built, boasting a size that is about 75% of a letter-sized sheet of paper with 1.2 trillion transistors, 400,000 processor cores, and 18 gigabytes of on-chip SRAM.
“This is a huge validation of the research we’ve been doing,” said Kumar in the article. "We like the fact that there is commercial interest in something like this.”
Despite the size, Kumar believes that the silicon interconnect fabric approach has advantages over Cerebras' wafer-scale engine. Firstly, it "allows a designer to mix and match technologies, and use the best manufacturing process for each." Cerebras' monolithic approach would mean picking the best process for a subsystem and using them for other components even if it is not ideal. Additionally, Cerebras could be limited in the amount of memory it puts on the processor.
"They have 18 gigabits of SRAM on the wafer." Kumar adds. "Maybe that’s enough for some models today, but what about models tomorrow and the day after?”
Kumar is also affiliated with the CSL
Check out the article from IEEE Spectrum here