Saving chips from an untimely demise, and winning an award in the process

Electrostatic discharge (ESD) events can be devastating events for integrated circuits (ICs), but a new testing method developed by ECE graduate students Nathan Jack and Vrashank Shukla gives insight on the integrity of ICs under test. Last September Jack and Shukla won the best student paper award for their paper titled, “Investigation of Current Flow During Wafer-Level CDM Using Real-Time Probing,” at the EOS/ESD Symposium held in Reno, Nevada. The symposium is the leading international technical venue for presenting the latest in ESD.

The paper, which was co-authored by ECE Professor Elyse Rosenbaum, examines the stress generated within a chip during an ESD event by using a modified testing setup that allows the chip to be stressed and probed simultaneously. New computer simulation techniques were also developed and employed to help interpret the measurement results.

One model of ESD events is the charged device model (CDM), which simulates the charge/discharge events that can occur during production. An example of a CDM event is the stress a chip feels when it has been charged up through friction and then comes into contact with grounded metal, thereby quickly discharging the chip.

“In a production environment, a chip could be moving down a conveyer belt or sliding down a tube, get charged up and touch something and discharges,” Shukla said. “In this case, the chip could be unintentionally destroyed.”

Chips are designed with built-in ESD protection to help them survive such an event. In order to ensure that chips are ESD robust, they are intentionally stressed on test machines. Typically this stress is applied to packaged devices, but is also often applied to unpackaged, wafer-level devices.

Traditionally, wafer-level CDM tests involve the wafer being placed on a chuck that is grounded, and a printed circuit board field plate is suspended over the wafer with an insulator between the two. A voltage is then applied to the field plate to build up the capacitance between the plate and the wafer. Then a probe needle is lowered to contact the pad on the wafer to discharge it.

While this configuration works well for applying a stress, it does not allow access to the wafer for real-time probing of the device. So, Jack looked at changing the test configuration setup by placing the PCB field plate underneath the chip instead of directly above it. The new configuration makes it possible to measure the real-time differential voltages generated within the chip during the ESD event.

“No one had ever measured nodes internally during a discharge event. Because the package was in the way, you couldn’t probe the chip,” Jack said.

Simultaneously, Shukla developed computer simulation techniques to predict what stress would be developed inside the chip during the ESD event. The measurement and simulation showed close agreement, and the simulations were essential for understanding the measurement results.

Both Jack and Shukla were proud that their work was recognized so highly at the symposium.

“It feels really good. It’s a recognition of our hard work, and it also feels good that the ESD symposium is the premier symposium in our field,” Shukla said. “It is nice to present your work in an audience like this.”

Jack added, “The people who chose our paper are the leaders in industry, and they obviously thought it was valuable. So it’s good to know they thought it was important.”

Recently, Jack and Shukla were asked to submit an extended version of this work as an invited paper in IEEE Transactions on Materials and Devices Reliability, a leading journal focused on research pertaining to the creation of reliable electronic materials and devices.

Rosenbaum said she was pleased that her students won the best student paper award at the symposium and that they were invited to submit an extended version of the paper to one of the top journals in the field. “I expect the excellent work of Nathan and Vrashank to have a major impact on the adoption of wafer-level test methods for CDM-ESD qualification,” she said.